The present invention arose in conjunction with the development of a multiplexer wherein three digital streams were multiplexed together onto a single high speed line. At the demultiplexed end, a synchronous one-third rate clock was needed to demultiplex the high speed data into three streams at one-third the high speed rate. The high speed clock was symmetric, and the divide by three divider circuit also had to have a symmetric output. That is, the output had to have a 50% duty cycle, with the output clock signal having a high state 50% of the time, and a low state the remaining 50% of the time.
Divide by three digital clock dividers are known, but do not have a symmetric output. One alternative is to generate a signal of twice the clock rate frequency and then perform a divide by six operation. This alternative is objectionable however because it requires too much hardware and logic operation, particularly at the higher, doubled rate. Another alternative is the use of a phase locked loop operating at one-third the fundamental frequency of the clock. This is basically an analog technique, however, and would require a large amount of hardware.